The present invention relates to a semiconductor memory device and, more particularly, to a multi-valued flash memory, a multi-valued EEPROM, and a multi-valued EPROM.
As one of EEPROM memory cells, a memory cell having a MOSFET structure in which a charge storage layer (floating gate) and a control gate are stacked on a semiconductor substrate is known. In general, data "0" or "1" is stored in accordance with the charge amount stored in the floating gate, and 1-bit data is stored in one cell. To realize a high-density EEPROM, a multi-valued storage method of storing multibit data in one cell is known. For example, in a 4-valued storage method, to store data "0", "1", "2", and "3" in one cell, four charge amounts corresponding to these data are stored in the floating gate.
An example of the data storage state will be explained using the 4-valued method. The neutral state is the state wherein the charge amount of the floating gate is 0, and the erase state is the state wherein positive charges are stored in the neutral state. The erase state corresponds to data "0". For example, data is erased by applying a high voltage (up to 20V) to the substrate and setting the control gate at 0V. The data "1" state is the state wherein negative charges are stored in the neutral state. The data "2" state is also the state wherein negative charges are stored in the neutral state but the negative charge amount is larger than in the data "1" state. In the data "3" state, the negative charge amount is much larger. For example, during a write, the substrate and the source and drain are set at 0V, and the control gate is set at a high voltage (up to 20V) to store negative charges in the floating gate and write data "1", "2", and "3". During a write, the substrate is set at 0V, the source and drain are set at 10V, and the control gate is set to a high voltage (up to 20V) to maintain the charges in the floating gate and store data "0" in the memory cell. This operation realizes four write states ("0", "1", "2", and "3") in the memory cell.
The write state of the memory cell is checked by applying a predetermined read voltage to the control gate and detecting whether a current called a cell current flows through the channel of the memory cell. The four write states can be determined by preparing three read voltages. In the memory cell flowing the cell current, the cell current increases the source voltage because a parasitic resistance exists between the source and ground voltage.
As one of multi-valued EEPROMs, an EEPROM in which multibyte data are written at once as multi-valued data in the memory cell is known (Jpn. Pat. Appln. KOKAI Publication No. 7-93979). To shorten the write time, data are written at once, and thus this EEPROM comprises a plurality of data memory circuits for storing control data for writing multi-valued data in each memory cell. To control the write state with high precision, e.g., the write state of the memory cell is detected after a write (write verify). For an insufficiently written memory cell, the control data of the data memory circuit is converted to apply a write voltage for enhancing a write in only this memory. Using the converted control data, data is written again. A write and write verify are continuously performed until data are satisfactorily written in all selected memory cells. In a read, similar to a write, data are also read out at once in units of a plurality of bytes in order to shorten the read time. The source of each memory cell is connected to a common source line.
In this EEPROM, the cell current greatly increases the common source line voltage in a read or write verify. This voltage depends on the number of memory cells flowing the cell current and the data pattern of a memory cell subjected to a simultaneous read or write verify. For this reason, there is a problem that the memory cell state cannot be accurately detected.
For example, when a voltage of 1V or more is applied to the control gate of a memory cell whose threshold voltage is 1V, the cell current should flow. However, the cell current flowing through memory cells other than this memory cell makes the common source line voltage float, and no cell current may flow through the memory cell whose threshold voltage is 1V. Particularly in the multi-valued memory cell, floating of source line voltage is a serious problem because a read and write must be controlled with high accuracy.
In the conventional memory, therefore, the memory cell state cannot be detected with high accuracy due to an increase in source line voltage caused by the flowing cell current.
The present invention has been made in consideration of the above situation, and its object is to provide a semiconductor memory device capable of detecting the memory cell state with high precision.